The present invention relates generally to design automation, and relates more particularly to the physical synthesis of large-scale, high-performance circuits.
Physical synthesis converts a logical description of an integrated circuit (IC) design into a physical layout. Two particular physical synthesis techniques are conventionally used to convert descriptions of large-scale ICs: a flat synthesis approach and a hierarchical approach.
The flat synthesis approach synthesizes all gates in the logical description at one time. This provides for global optimization and often results in a good layout. However, flat synthesis does not allow for floorplanning, and thus offers little user control. Thus, flat synthesis may not be the best approach for large-scale designs, in which a single objective flat placement and optimization may not be optimal. For example, control logic regions of the design may require more empty space than datapath regions, or critical regions may need to be placed in certain areas of the circuit. Although movebound constraints may be used to guide accommodate these requirements, the parameters for the movebound constraints are generally difficult to generate.
The hierarchical approach separates the gates in the logical description into multiple partitions, and then synthesizes each partition individually. Although the hierarchical approach offers greater user control over the critical path and critical regions of the circuit, the boundary logic is not optimized because partition boundaries prevent cross-boundary optimization. In addition, the quality of the synthesis relies heavily on the locations and timing assertions that are used to assign the boundary pins that define the boundaries of each partition. The locations in particular are difficult to assign optimally.